1. Field of the Invention
The present invention generally relates to an information processing apparatus and, more particularly, to an information processing apparatus with a cache memory.
2. Description of the Related Art
An information processing apparatus such as a computer or a word processor often includes a main memory with a relatively large capacity divided into a plurality of blocks each having a predetermined size, and a cache memory, with a capacity smaller than that of the main memory, for achieving high-speed processing. In such an information processing apparatus, the memory contents are stored in the cache memory from the main memory in units of blocks divided to each have a predetermined size, and are returned from the cache memory to the main memory. If the cache memory is driven by a 32-bit microprocessor, the predetermined size corresponds to 4 words (16 bytes).
In a conventional information processing apparatus, a microprocessor can access only one word in the cache memory at a time. For this reason, an application, e.g., in which a plurality of arbitrary words are simultaneously accessed to increase a processing speed, cannot be performed, thus preventing high-speed processing.